The present invention relates to a mask and a method for manufacturing a semiconductor device.
In the lithography process in the prior art, a photoresist is first applied onto the front surface of a wafer, exposed with the main pattern for the mask by employing an exposure apparatus and then development is implemented to form a resist pattern on the wafer.
However, in photolithography implemented by utilizing excimer light, which is already adopted in mass production of semiconductor devices, the degree of transparency of the photoresist is increased to allow the excimer light to be transmitted. In addition, a shorter wavelength, as is the case with excimer light, causes the light reflectance of the lower layer film in the photoresist to increase. Consequently, even a minute difference in the energy of radiated light tends to affect the dimensions of the resist pattern more readily. In other words, a relative difference in the radiated light energy is present between an area where the pattern is dense and an area where the pattern is sparse.
As a result, there may be marked differences in the dimensions of elements in different portions of a resist pattern achieved through the lithography process in the prior art, resulting in the dimensions of the resist having partially deviating from the desired dimensional specifications. The radiated light energy in this context refers to the quantity of light radiated per unit area, and normally, it is expressed using the unit J(mJ). In addition, the dimensions of the pattern refer to the dimensions of pattern elements constituting the pattern.
FIGS. 9xcx9c12 illustrate the problem of the lithography process in the prior art discussed above. As shown in FIG. 9, the dimensions of elements in the outermost peripheral area are smaller than the dimensions of elements in the densely patterned area in a contact-hole pattern formed through the lithography process in the prior art. The data presented in FIG. 11 in regard to a contact pattern formed through the lithography process in the prior art substantiate the inconsistent formation of the contact pattern, as illustrated in FIG. 9. In addition, as shown in FIG. 10, in a line and space pattern formed through the lithography process in the prior art, the dimensions of elements in the outermost peripheral area are smaller than the dimensions in the densely patterned area due to the proximity effect. The data presented in FIG. 12 in regard to a line and space pattern formed through the lithography process in the prior art substantiate the inconsistent formation of the line and space pattern illustrated in FIG. 10.
An object of the present invention, which has been completed by addressing the problem of the lithography process in the prior art discussed above is to provide a new and improved mask and a new and improved method for manufacturing a semiconductor device, through which consistency in the dimensions of a resist pattern is achieved without adversely affecting other processes implemented on the wafer. Another object of the present invention is to provide a new and improved mask and a new and improved method for manufacturing a semiconductor device, through which consistency in the resist pattern dimensions is achieved without resulting in a reduction in throughput or an increase in cost.
Yet another object of the present invention is to provide a new and improved mask and a new and improved method for manufacturing a semiconductor device through which characteristics defects of semiconductor elements can be reduced and an improvement in the semiconductor device yield is achieved.
In order to achieve the objects described above, according to the present invention as defined in claims 1 through 3, the following structures are adopted in a mask employed in lithography, having a main pattern drawn thereupon with a specific arrangement, which is transferred onto a preset element formation area on a wafer and an additional pattern formed around the main pattern which adjusts the exposure quantity.
Namely, in the present invention as defined in claim 1, the additional pattern contains a shift pattern that manifests a specific quantity of shift relative to the main pattern. In the invention as defined in claim 1 adopting this structure, the quantity of exposure of the resist is adjusted by the additional pattern. In addition, in the invention as defined in claim 1, by achieving the adjustment over the specific degree of shift, the formation of the resist pattern in the area surrounding the preset element formation area on the wafer, which is attributable to the additional pattern, can be controlled without having to change the dimensions of the additional pattern.
Thus, according to the present invention as defined in claim 1, consistency in the dimensions of the resist pattern in the preset element formation area is achieved and, at the same time, any adverse effects that may manifest due to the presence of the additional pattern after the lithography process (e.g., formation of stages in the area surrounding the preset element formation area) can be suppressed. As a result, according to the present invention as defined in claim 1, an improvement in the lithographic precision is achieved without affecting the other processes implemented on the wafer so that a reduction in the characteristics defects of semiconductor elements and an improvement in the semiconductor device yield are achieved.
The exposure quantity in this context refers to the quantity of energy per unit area of light radiated on the resist which is a photosensitive material, in the area onto which the main pattern is transferred. In addition, the term xe2x80x9cexposure quantityxe2x80x9d is not necessarily used to refer to the quantity of light energy only, and it may be used to indicate the quantity of energy of any of various radiations such as x-rays, electron beams, ion beams or radioactive rays.
It is to be noted that as in the invention defined in claim 2, the shift pattern may assume a structure having an arrangement rule identical to that of the specific arrangement. The arrangement rule in this context refers to the rule adopted in arranging pattern elements in the pattern.
In addition, in the present invention as defined in claim 3, the additional pattern contains a frame pattern that surrounds the periphery of the main pattern. In the invention defined in claim 3, the exposure quantity for the resist is adjusted by the additional pattern containing the frame pattern. Unlike the main pattern, the frame pattern is simple and large.
Consequently, according to the invention as defined in claim 3, the problem of insufficient exposure quantity at the outermost peripheral area of the main pattern can be eliminated with a high degree of reliability. Furthermore, according to the invention as defined in claim 3, an inexpensive mask can be formed with ease. As a result, by adopting the invention as defined in claim 3, which achieves both a reduction in the manufacturing cost and an improvement in the lithographic precision, a reduction in the price of the semiconductor device is realized in addition to reducing characteristics defects of semiconductor elements and increasing the semiconductor device yield.
Also, in order to achieve the objects described above, according to the present invention as defined in claim 4, a mask that is utilized in lithography, having drawn thereupon at least a main pattern with a specific arrangement which is transferred onto a preset element formation area on a wafer, adopts a structure having an additional pattern for adjusting the exposure quantity drawn toward the inside relative to the main pattern in an area where the pattern is sparse. The area where the pattern is sparse in this context refers to an area where the element pattern is spread out such as, for instance, an outermost peripheral area of the pattern or an area where the pattern is isolated.
According to the invention defined in any of claims 1 through 4, the shape of the additional pattern can be designed by taking into consideration the effect on the wafer processing implemented before and after the lithography process. By designing the shape of the additional pattern in this manner, problems such as the element pattern being formed inaccurately, an extremely small margins in production and degradation in the element characteristics can be minimized.
Furthermore, according to the invention as defined in any of claims 1 through 4, the additional pattern can be designed to be formed at an optically appropriate position for exposure. By designing the additional pattern to be formed at an appropriate position in this manner, the dimensional differences in the pattern elements in dense areas and in sparse areas in the preset element formation area can be kept to a minimum.
Moreover, in order to achieve the objects described above, according to the present invention as defined in claim 5, a method for manufacturing a semiconductor device includes a lithography process which utilizes a mask as disclosed in any of claims 1, 2, 3 and 4. As explained above, since consistency in the dimensions of the resist pattern is achieved in the invention as defined in claims 1 through 4, the invention as defined in claim 5 provides a method for manufacturing a semiconductor device that achieves a reduction in characteristics defects of semiconductor elements and an improvement in the semiconductor device yield.